This invention relates to the field of application-specific integrated circuits (ASICs) and systems and methods of reducing power consumption in the same.
Clock gating can be used to “turn off” parts of a circuit to reduce the power consumption of a device. A clock signal passes through a logic circuit that can selectively block, or gate, the clock signal. When the clock signal is blocked, logic driven by the gated clock signal suspends operation and does not consume any dynamic power. The amount of power savings is related to the amount of logic that is effectively turned off. The higher the gating is done on the clock tree, a larger portion of the clock network is turned off and the more power is saved. If the clock is gated at the leaf-cell level (for example, immediately before the clock input to a register), very little power is saved because the whole clock network still toggles.
Structured ASICs are devices that have some predetermined circuit characteristics, but that are also customizable to some degree. For example, a structured ASIC may include a two-dimensional array (fabric) of many relatively small logic elements (referred to herein as hybrid logic elements or HLEs). The basic circuitry of these HLEs is always the same or substantially the same, and is provided by a subset of the masks that are used to make the structured ASIC. Accordingly, the masks in this subset can be always the same or substantially the same. The overall function(s) performed by an HLE can be customized to some extent by customizing one or more additional masks used to make a particular structured ASIC product. Similarly, connections to, from, and/or between HLEs can be customized by customizing additional masks used to make the product. Because the structured ASIC always has the same basic circuitry, the task of designing it to perform particular tasks is greatly simplified, speeded up, increased in reliability, and reduced in cost. An entire ASIC does not have to be designed “from scratch.” Instead, only the customizable masks have to be designed.
A possible use of structured ASIC technology is to produce ASICs that are functionally equivalent to programmed field-programmable gate arrays (“FPGAs”). After a logic design has been adequately “proven” in an FPGA, the design may be “migrated” to a structured ASIC. In structured ASICs, the disposition (location or arrangement) of circuit functions (e.g., logic functions) on the structured ASIC can be quite different from the disposition of those functions on the FPGA to which the structured ASIC is supposed to be functionally equivalent. Thus, it may not be possible to simply duplicate on the structured ASIC the architecture of the related FPGA circuitry for routing, gating, or distributing clock signals to the functional circuitry. Accordingly, it is difficult to transport the efficacy of the FPGA clock gating circuitry to the structured ASIC. Additionally, designing completely customized clock gating circuitry for a structured ASIC is not a good approach because of the cost and complexity of the design task.
It is therefore desirable to have efficient methods and circuits for clock gating in a structured ASIC with minimal design effort.